Chimera v1.4.0 Change Log

It's good to see that the Chameleon team has started porting some of the changes I made from Chimera to the Chameleon 2.0 RC5 trunk. They recently did a major update and added significant new features in trunk revision 833. Some of the changes were enhanced and fixed Sandy Bridge support amongst others. So I went back and integrated my changes into that trunk version and created Chimera v1.4.0.

Starting with this version I will list in detail all changes I've made. All lines starting with a dash will be the name of the affected file starting at the branch root.

General fixes and enhancements:

Chimera 1.4.0 Installer available
at tonymacx86.com/downloads

- CHANGES
        Fixed typos
- doc/BootHelp.txt
        Added UseKernelCache=Yes|No
        Reworded some options
- TODO
        Fixed typos
- i386/boot2/boot.c
        Fixed typos in comments
        Reordered keys according to source file name
- i386/doc/README
        Fixed typos
- i386/libsaio/acpi_patcher.c
        In switch (Platform.CPU.Model)
                Removed nonexistent CPU model case 0x0D: // ?
                Redid comments for all case CPU_MODEL_ to provide actual CPU model names
- i386/libsaio/ati.c
        In static radeon_card_info_t  radeon_cards[]
                Removed duplicate blank lines
                Removed duplicate "ATI Radeon HD 5400 Series"
                Added additional AMD cards:
                        { 0x6739, 0x21F81458, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850",
kDuckweed },
                        { 0x6719, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950
                           Series", kNull },
                        { 0x6738, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870 Series", 
kDuckweed },
                        { 0x6739, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850 Series", 
kDuckweed },
                        { 0x673E, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6790 Series",
  kNull },
                Changed { 0x6718, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6900
                          Series", kNull },
                 to { 0x6718, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970 Series",
kNull },
- i386/libsaio/cpu.c
        Updated /* Mobile CPU */ to use MSR_IA32_PLATFORM_ID instead of a hex value
        Rearranged DBG info at end and added additional info
- i386/libsaio/cpu.h
        Added #define MSR_IA32_PLATFORM_ID 0x17
- i386/libsaio/memvendors.h
        Removed extra spaces in fromt of { 0, 0x01, "AMD"},
- i386/libsaio/nvidia.c
        Added comments to add device id blocks like // 0040 - 004F, // 0050 - 005F, etc.

        Added workaround code for GT 430 & 9600M GT memory detection from valv

        Added GT 420 to GT 430 & 9600M GT memory detection work around
        Added the following new device IDs from valv and Linux driver (some are already in v1.3.0):
                { 0x10DE0410, "GeForce GT 330" },
                { 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
                { 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
                { 0x10DE053E, "GeForce 7025 / nForce 630a" },
                { 0x10DE05ED, "Quadroplex 2200 D2" },
                { 0x10DE05F8, "Quadroplex 2200 S4" },
                { 0x10DE05FF, "Quadro FX 3800" },
                { 0x10DE0601, "GeForce 9800 GT" },
                { 0x10DE0603, "GeForce GT 230" },
                { 0x10DE060F, "GeForce GTX 285M" },
                { 0x10DE0619, "Quadro FX 4700 X2" },
                { 0x10DE061B, "Quadro VX 200" },
                { 0x10DE062D, "GeForce 9600 GT" },
                { 0x10DE062E, "GeForce 9600 GT" },
                { 0x10DE0631, "GeForce GTS 160M" },
                { 0x10DE0632, "GeForce GTS 150M" },
                { 0x10DE0635, "GeForce 9600 GSO" },
                { 0x10DE0637, "GeForce 9600 GT" },
                { 0x10DE0638, "Quadro FX 1800" },
                { 0x10DE063A, "Quadro FX 2700M" },
                { 0x10DE0651, "GeForce G 110M" },
                { 0x10DE0653, "GeForce GT 120M" },
                { 0x10DE0654, "GeForce GT 220M" },
                { 0x10DE0656, "GeForce 9650 S" },
                { 0x10DE065F, "GeForce G210" },
                { 0x10DE06E2, "GeForce 8400" },
                { 0x10DE06E3, "GeForce 8400 SE" },
                { 0x10DE06E6, "GeForce G100" },
                { 0x10DE06E7, "GeForce 9300 SE" },
                { 0x10DE06FB, "Quadro FX 370M" },
                { 0x10DE07E0, "GeForce 7150 / nForce 630i" },
                { 0x10DE07E1, "GeForce 7100 / nForce 630i" },
                { 0x10DE07E2, "GeForce 7050 / nForce 630i" },
                { 0x10DE07E3, "GeForce 7050 / nForce 610i" },
                { 0x10DE07E5, "GeForce 7050 / nForce 620i" },
                { 0x10DE0844, "GeForce 9100M G" },
                { 0x10DE0845, "GeForce 8200M G" },
                { 0x10DE0846, "GeForce 9200" },
                { 0x10DE0847, "GeForce 9100" },
                { 0x10DE0848, "GeForce 8300" },
                { 0x10DE0849, "GeForce 8200" },
                { 0x10DE084A, "nForce 730a" },
                { 0x10DE084B, "GeForce 9200" },
                { 0x10DE084C, "nForce 980a/780a SLI" },
                { 0x10DE084D, "nForce 750a SLI" },
                { 0x10DE084F, "GeForce 8100 / nForce 720a" },
                { 0x10DE0860, "GeForce 9400" },
                { 0x10DE0861, "GeForce 9400" },
                { 0x10DE0862, "GeForce 9400M G" },
                { 0x10DE0863, "GeForce 9400M" },
                { 0x10DE0864, "GeForce 9300" },
                { 0x10DE0865, "ION" },
                { 0x10DE0866, "GeForce 9400M G" },
                { 0x10DE0867, "GeForce 9400" },
                { 0x10DE0868, "nForce 760i SLI" },
                { 0x10DE086D, "GeForce 9200" },
                { 0x10DE086E, "GeForce 9100M G" },
                { 0x10DE086F, "GeForce 8200M G" },
                { 0x10DE087A, "GeForce 9400" },
                { 0x10DE0A22, "GeForce 315" },
                { 0x10DE0A2B, "GeForce GT 330M" },
                { 0x10DE0A2C, "NVS 5100M" },
                { 0x10DE0A2D, "GeForce GT 320M" },
                { 0x10DE0A35, "GeForce GT 325M" },
                { 0x10DE0A3C, "Quadro FX 880M" },
                { 0x10DE0A64, "ION" },
                { 0x10DE0A67, "GeForce 315" },
                { 0x10DE0A68, "GeForce G105M" },
                { 0x10DE0A69, "GeForce G105M" },
                { 0x10DE0A6A, "NVS 2100M" },
                { 0x10DE0A6C, "NVS 3100M" },
                { 0x10DE0A6E, "GeForce 305M" },
                { 0x10DE0A6F, "ION" },
                { 0x10DE0A70, "GeForce 310M" },
                { 0x10DE0A71, "GeForce 305M" },
                { 0x10DE0A72, "GeForce 310M" },
                { 0x10DE0A73, "GeForce 305M" },
                { 0x10DE0CA0, "GeForce GT 330 " },
                { 0x10DE0CA2, "GeForce GT 320" },
                { 0x10DE0CA4, "GeForce GT 340" },
                { 0x10DE0CA7, "GeForce GT 330" },
                { 0x10DE0CAC, "GeForce 315" },
                { 0x10DE0CAF, "GeForce GT 335M" },
                { 0x10DE0CB0, "GeForce GTS 350M" },
                { 0x10DE0CBC, "Quadro FX 1800M" },
                { 0x10DE0DE0, "GeForce GT 440" },
                { 0x10DE0DE5, "GeForce GT 530" },
                { 0x10DE1040, "GeForce GT 520" },
                { 0x10DE1050, "GeForce GT 520M" },
                { 0x10DE1081, "GeForce GTX 570" },        Updated with model name
                { 0x10DE1082, "GeForce GTX 560 Ti" },   Updated with model name
                { 0x10DE1088, "GeForce GTX 590" },
                { 0x10DE10C3, "GeForce 8400 GS" },
                { 0x10DE1200, "GeForce GTX 560 Ti" },
                { 0x10DE1244, "GeForce GTX 550 Ti" },
                { 0x10DE1245, "GeForce GTS 450" },
- i386/libsaio/platform.h
        Added additional info to comments for #define CPU_MODEL_
- i386/libsaio/smbios.c
        Updated comments on all case CPU_MODEL_ to provide actual CPU model names
- i386/libsaio/smbios_getters.c
        Updated comments on all case CPU_MODEL_ to provide actual CPU model names
        Removed all references to nonexistent CPU models:
                case 0x0D: // ?
                case 0x19: // Intel Core i5 650 @3.20 Ghz
        Added workaround to not calculate qpibusspeed for LGA 1155 and LGA 1156 CPUs
           and report a sane value
        Added Xeon model detection and reporting to CPU_MODEL_FIELDS:
        Broke out case CPU_MODEL_SANDY_XEON: to report Xeon CPU

Chimera Specific Changes:

- i386/boot2/Makefile
        git revision workaround
- i386/boot2/prompt.c
        Changed Chameleon to Chimera
- i386/libsaio/fake_efi.c
        Changed FIRMWARE_VENDOR from Chameleon 2.0.0 to Chimera 1.4.0

For bug reporting, feature requests, and general feedback please use the Chimera forum. 

-MacMan & tonymacx86 

For discussions on this and other topics, register today at tonymacx86.com!

Chimera v1.1.0 Source Pedigree and Enhancements

Most of you know about Chimera based on the announcement we made on the tonymacx86 Blog. A few of you are interested in what I did and what is different in Chimera compared to the Chameleon trunk. Without getting too deep into the code, I will attempt to explain in general terms these differences. I will be explaining the changes based on v1.1.0 r753 as this was the first source version released.

I wanted to start with the trunk version as I know that code is clean and stable. The first few things I did was fix a few spelling errors in TODO and i386/doc/README. No big deal, but I think something that was overdue. Next, I went through all of the source files. I cleaned up the comments for readability to make sure they all lined up properly. Here are the list of files that I did this to:

i386/boot2/boot.h
i386/libsa/memory.h
i386/libsaio/bootstruct.h
i386/libsaio/cpu.h
i386/libsaio/fdisk.h
i386/libsaio/memvendors.h
i386/libsaio/nvidia.c
i386/libsaio/smbio_patcher.c
i386/libsaio/smbio_patcher.h
i386/libsaio/spd.c

Again, not a big deal, but to make it easier for me to read the code.

So now it was time to start merging features. I decided to start with Kabyl's ATI support. For this I had to update doc/BootHelp.txt to include his 2 new boot keys. I also added the two actual boot keys to i386/boot2/boot.h. Then in i386/libsaio/, I replaced the trunk ati.c with Kabyl's. Added his ati_reg.h and removed ati.h. Then I added Kabyl's changes to pci.c, pci.h and pci_setup.c.

Next was merging valv's NVIDIA changes. For that I added 2 new NVIDIA keys to i386/boot2/boot.h. Then in i386/libsaio/nvidia.c I used a combination of trunk, valv and new device ID's I could find to support as many cards as possible in NVKnownChipsets. I then used valv's #define NVIDIA_ROM_SIZE 0x20000 and  static uint8_t default_dcfg_0[], static uint8_t default_dcfg_1[], and static uint8_t default_NVPM[]. I also used his improved video RAM detect code, workaround code for gt 430 & 9600M GT and support for user supplied @0,display-cfg and @1,display-cfg keys.

The final changes were in adding Sandy Bridge support. For this I used some of valv's code but added a bunch of my own. From valv I used his setup features which required using his CPU Features in platform.h. Where I also took his #define bit definitions. Then in cpu.h I used his additional MSR defines and static inline __attribute__((always_inline)) void wrmsr(unsigned val, msr_t msr), typedef struct msr_struct and static inline __attribute__((always_inline)) msr_t rdmsr(unsigned val). And finally some of his CPU debug messages and formatting at the end of cpu.c.

So as documented above, I've reused a bunch of code from Kabyl and valv. Now let's discuss the changes I did. The first thing is in platform.h where I added #define CPU_MODEL_DUNNINGTON 0x1D and #define CPU_MODEL_SANDY_BRIDGE 0x2A. Then in cpu.c I changed all p->CPU.Model from using hex values to defined values from platform.h. I did this to make troubleshooting easier- as I don't know all of the CPUs model codes by heart. I then removed p->CPU.Model == 0x1f as I can find no reference anywhere of this CPU model. I then went and redid  if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) to add Sandy Bridge support.

When testing the code I found that cpu.c was reporting 8 cores and 16 threads for Core i and Sandy Bridge CPUs. It took a bit of digging but I found that in the original code the value for them was being extracted from a Machine Specific Register (MSR) that was returning the Maximum # of addressable IDs for logical processors in this physical package and Maximum # of addressable IDs for processors cores in this physical package. So I did a bunch of testing and research and found that there is an undocumented MSR, MSR_CORE_THREAD_COUNT that will return the correct values. I used that in Chimera v1.0.0 r750 but we soon learned that that isn't a valid MSR on Penryn or earlier CPU models.  So in v1.1.0 I added the following code to set the number of cores and threads correctly:

if ((p->CPU.Vendor == 0x756E6547 /* Intel */) &&
    (p->CPU.Family == 0x06) && (p->CPU.Model >= 0x1a)){

msr = rdmsr64(MSR_CORE_THREAD_COUNT);            // Undocumented MSR

p->CPU.NoCores = bitfield((uint32_t)msr, 31, 16);     // Get actual values

p->CPU.NoThreads = bitfield((uint32_t)msr, 15,  0);   // Get actual values

} else {  // Use previous method for Cores and Threads

p->CPU.NoThreads = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);

p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;

}

I also changed the Mobile CPU test from using a hex value to the MSR name MSR_IA32_Platform_ID.

Next up was  i386/libsaio/acpi_patcher.c. Here I removed the case 0x0D: statement as this CPU model family Dothan, pre-dates the Core family. I also added a case CPU_MODEL_SANDY_BRIDGE: and added comments for what each CPU model covers. So for example:

 case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm).

In  i386/libsaio/spd.c I changed smbus_controllers[] to report "5 Series" instead of "P55" and added {0x8086, 0x1C22, "6 Series",read_smb_intel }.

The final source file to modify was i386/libsaio/smbios_patcher.c. Here I also added better CPU comments like in acpi_patcher.c. I also changed all reference of "Apple Computer, Inc." to "Apple Inc.",  fixed MacPro3,1 "SMboardproduct" and MacPro4,1 "SMboardproduct" to use the correct board numbers and finally reorganized the system order to MacBook, MacBook Pro, mini, iMac8,1, iMac11,1 MacPro3,1 and MacPro4,1. The I removed all instances of case 0x19: // Intel Core i5 650 @3.20 Ghz as I couldn't find any references to this CPU model and the description didn't match the model value. I also removed  case 0x0D:  and added case CPU_MODEL_SANDY_BRIDGE:. Other changes were adding DBG("FSBFrequency %d\n", Platform.CPU.FSBFrequency); and changing DBG("qpimult %x\n", qpimult); to display in hex instead of decimal. The final changes were hard coding the Processor Interconnect speed for Sandy Bridge CPUs to 4.8 GT/s instead of the incorrect calculated value. Finally I redid sm_get_cputype to correctly handle all possible CPU types, including Xeons.

In addition, I took from tonymacx86.com forum user AndyStubbs his code additions to support the AMD Radeon HD 6000 cards and his fix to i386/libsaio/smbios_patcher.c for DMI table overflow on Sandy Bridge systems. Thanks Andy.

Going forward the plan is to keep Chimera updated with trunk revisions in addition to adding new features and bug fixes.

I will post further code changes when I release new versions. So stay tuned for updates.

Further Reading:
Chimera Source
Chimera: Unified Chameleon Bootloader
Chimera Now An Official Chameleon Branch
Chimera 1.1 Update
Chimera 1.3 Update
Chimera at tonymacx86 Wiki