Enhanced 10.8.4 Kernel For Haswell

Since OS X 10.8.5 or Mavericks 10.9 has not been released, I decided to enhance the 10.8.4 kernel to allow it to boot on Haswell based machines.

You can download the source for the 10.8.4 kernel at http://www.opensource.apple.com/tarballs/xnu/xnu-2050.24.15.tar.gz

Here are the changes I made:

In the file osfmk/i386/cpuid.h

Added:
#define CPUID_MODEL_HASWELL 0x3C

In the file osfmk/i386/cpuid.c

Added:
case CPUID_MODEL_HASWELL:

The pre-built kernel in a handy installer is now available at
http://www.tonymacx86.com/379-haswellhelper-enhanced-10-8-4-kernel-now-available.html

Enjoy.

Customizing SSDT: Power Management Optimization on 10.7.4

With the release of SSDTs in MultiBeast, I decided to limit the Overclocked SSDT to a maximum clock of 4.2 GHz since that is the maximum that About This Mac can report using auto detection.

Over the past few days, numerous users have been asking how to customize their SSDT to run at a higher clock rate, and how to see more P-states on a non-overclocked system. This post aims to explain the SSDT and how to customize it.

Lets look at the first block of code:

    External (\_PR_.CPU7, DeviceObj)
    External (\_PR_.CPU6, DeviceObj)
    External (\_PR_.CPU5, DeviceObj)
    External (\_PR_.CPU4, DeviceObj)
    External (\_PR_.CPU3, DeviceObj)
    External (\_PR_.CPU2, DeviceObj)
    External (\_PR_.CPU1, DeviceObj)
    External (\_PR_.CPU0, DeviceObj)

This block defines how many real or hyper-thread CPU's are available. So in this example, we are defining up to 8 CPUs. If your CPU has less (Core i3 or Core i5) it is safe to delete External (\_PR_.CPU4, DeviceObj) thru External (\_PR_.CPU7, DeviceObj). But then you will need to delete the corresponding entries Scope (\_PR.CPU4) thru Scope (\_PR.CPU7) at the end of the SSDT.

Let's look at the next section:

    Scope (\_PR.CPU0)
    {
        Name (APSN, 0x04)
        Name (APSS, Package (0x1B)
        {

Here we are defining the details for CPU0. The first line is assigning 0x4 to APSN which is an Apple-specific object. The next object APSS is also Apple-specific, but is defined the same as the ACPI object _PSS. The key thing in this line is Package (0x1B) as 0x1B defines in hexadecimal the number of definitions contained within. So 0x1B corresponds to 27 decimal. This means we have 27 states defined.

Next let's look at the top most entry but with comments added based on the ACPI Specification for _PSS:

            Package (0x06)
            {
                0x1068,   // CoreFreq
                Zero,        // Power
                0x0A,      //  TransitionLatency
                0x0A,      //  BusMasterLatency
                0x2A00,  // Control
                0x2A00   // Status
            },

From ACPI Specification- Section 8.4.4.2:

• CoreFreq. Indicates the core CPU operating frequency (in MHz).
• Power. Indicates the performance state’s maximum power dissipation (in milliWatts).
• TransitionLatency. Indicates the worst-case latency in microseconds that the CPU is unavailable during a transition from any performance state to this performance state.
• BusMasterLatency. Indicates the worst-case latency in microseconds that Bus Masters are prevented from accessing memory during a transition from any performance state to this performance state.
• Control. Indicates the value to be written to the Performance Control Register (PERF_CTRL) in order to initiate a transition to the performance state.
• Status. Indicates the value that OSPM will compare to a value read from the Performance Status Register (PERF_STATUS) to ensure that the transition to the performance state was successful. OSPM may always place the CPU in the lowest power state, but additional states are only available when indicated by the _PPC method.

So in our example CoreFreq is 0x1068 is 4200 or 4.2 GHz. It seems that Apple is ignoring the value for Power, though you can use the Power values from the motherboard's SSDT extract. I've found that TransitionLatency and BusMasterLatency are always 0x0A. Now for the final two values, 0x2A00 or 4200. In this case we ignore the two zeros and are only concerned with the two numbers. This is the value that will be displayed by MSRDumper. So when the system is running at 4.2 GHz MSRDumper will show the P-state as 42.

Ok now let's look at the next entry.

            Package (0x06)
            {
                0x1004,
                Zero,
                0x0A,
                0x0A,
                0x2900,
                0x2900
            },

So 0x1004 is 4100 or 4.1 GHz and 0x2900 translates to 41. Pretty simple. If you keep following down you will see that CoreFreq decrease by 0x64 or 100 for each state and Control and Status decrease by 1. The last entry will have a CoreFreq of 0x0640 and Control and Status will be 0x1000. This corresponds to 1600 or 1.6 GHz and 16, the minimum clock rate for a desktop Sandy Bridge CPU.

Now that that has been explained lets look at the next Scope.

Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Return (\_PR.CPU0.APSS)
        }
    }

All this is showing is that instead of repeating what we did for the CPU0, we can have the SSDT return what was defined for CPU0. Alternately, you can define individual P-states for each processor, but it is a very time consuming process. The way I've described is much easier and less work.

Finally we can discuss what we need to change when modifying the SSDT. If you remove P-states you must decrease the value in Name (APSS, Package (0x1B) to reflect the number of states deleted. The MultiBeast i7 SSDT has a maximum clock of 3.9 GHz. The means the top entry will look like this:

        Name (APSS, Package (0x18)
        {
            Package (0x06)
            {
                0x0F3C,
                Zero,
                0x0A,
                0x0A,
                0x2700,
                0x2700
            },

So the Package count went down by 3 from Package (0x1B) to  Name (APSS, Package (0x18) and the first package shows the CoreFreq of 0x0F3C is 3900 or 3.9 GHz and Control and Status are now 0x2700 or 39.

Likewise if you want to add states, remember to add 0x64 to each CoreFreq and 1 to Control and Status and make sure that the value in Name (APSS, Package (0x18) corresponds to the total number of P-states defined.

Something everyone should be aware of is that there is a limit to the number of entries that AppleIntelCPUPowerManagement can handle. If you define more P-states then you can use, like using the Overclock SSDT on a non-overclocked system, you will lose P-states at the bottom of the table. When I used the MultiBeast Overclock SSDT which has a maximum clock of 4.2 GHz on a system that can reach a maximum of 3.8 GHz you will see the following from MSRDumper:

MSRDumper PStatesReached: 16 23 24 25 26 27 38

Versus using the MultiBeast i7 SSDT where you will see:

MSRDumper PStatesReached: 16 17 18 19 20 21 35 36 37 

You may say what's the big deal? Well it relates to power consumption. The lower the P-state (CPU frequency) the lower the power consumption. So by using the Overclocked SSDT my power consumption will be higher which will cost me money in the long run.

I hope you found this information helpful!

-MacMan

Related Posts:
10.7.4 Power Management and Sandy Bridge CPUs
How To Test for SpeedStep on Sandy Bridge CPUs Using MSRDumper
Mac OS X 10.7.4 Update

UniBeast: Install Mac OS X Lion Using an All-In-One Bootable USB Drive

Building a Sandy Bridge CustoMac: Buyer's Guide

For discussions on this and other topics, register today at tonymacx86.com!

Chimera 1.8.0 Source

The Chimera 1.8.0 source is now available for downloading. Here is the link to the commit: http://forge.voodooprojects.org/p/chameleon/source/commit/1832/

There is a standalone installer, available at tonymacx86.com/downloads. For bug reporting, feature requests, and general feedback please use the Chimera forum.

-tonymacx86 & MacMan

Related Posts:
Chimera 1.8 Change Log
Chimera 1.8 Update: OS X 10.8 Mountain Lion Support

For discussions on this and other topics, register today at tonymacx86.com!

Chimera 1.8.0 Change Log

Here are the details on specifically what I changed in Chimera 1.8.0.

• Mountain Lion Boot Support:
Based on cparm's patch.

i386/boot2/boot.c
Changed all (checkOSVersion("10.7") to ((checkOSVersion("10.7")) || (checkOSVersion("10.8")))

i386/libsaio/bootstruct.c
Changed:
&& (gMacOSVersion[2] == '.') && (gMacOSVersion[3] == '7'))

To:
&& (gMacOSVersion[2] == '.') && ((gMacOSVersion[3] == '7') || (gMacOSVersion[3] == '8')))

• Fixed showing boot volume detail:

i386/boot2/gui.c
Changed:
shoWinfo = true

To:
shoWinfo = false

• Trunk Commit: 1827 Xcode 4.3 compile fix:

i386/util/fdisk/misc.c
Changed:
void
putshort(p, l)
void *p;
u_int16_t l;

To:
putshort(
void *p,
u_int16_t l)

• Added addtitional NVIDIA cards and fixed some card definitions using info from latest trunk, ErmaC branch and tonymacx86.com users:

i386/libsaio/nvidia.c
Added:
{ 0x10DE05E7, "Tesla C1060" },
{ 0x10DE061E, "Quadro FX 3700M" },
{ 0x10DE0621, "GeForce GT 230" },
{ 0x10DE062B, "GeForce 9800M GS" },
{ 0x10DE0655, "GeForce GT 120" },
{ 0x10DE06F1, "GeForce G105M" },
{ 0x10DE06FF, "HICx16 + Graphics" },
{ 0x10DE0840, "GeForce 8200M" },
{ 0x10DE0869, "GeForce 9400" },
{ 0x10DE08A0, "GeForce 320M" },
{ 0x10DE08A4, "GeForce 320M" },
{ 0x10DE0A26, "GeForce 405" },
{ 0x10DE0A27, "GeForce 405" },
{ 0x10DE0A38, "Quadro 400" },
{ 0x10DE0A76, "ION" },
{ 0x10DE0A7A, "GeForce 315M" },
{ 0x10DE0CA5, "GeForce GT 220" },
{ 0x10DE0CAC, "GeForce GT 220" },
{ 0x10DE1051, "GeForce GT 520MX" },
{ 0x10DE1084, "GeForce GTX 560" },
{ 0x10DE1087, "GeForce GTX 560 Ti 448 Cores" },
{ 0x10DE1089, "GeForce GTX 580" },
{ 0x10DE108B, "GeForce GTX 590" },
{ 0x10DE1091, "Tesla M2090" },
{ 0x10DE109B, "Quadro 7000" },
{ 0x10DE10C0, "GeForce 9300 GS" },
{ 0x10DE10D8, "NVS 300" },
{ 0x10DE1241, "GeForce GT 545" },
{ 0x10DE1243, "GeForce GT 545" },

Changed:
{ 0x10DE0CAC, "GeForce 315" }, to { 0x10DE0CAC, "GeForce GT 220" },
{ 0x10DE0DF4, "GeForce GT 450M" }, to { 0x10DE0DF4, "GeForce GT 540M" },
{ 0x10DE109A, "N12E-Q5" }, to { 0x10DE109A, "Quadro 5010M" },

• Added additional AMD/ATI Cards:

i386/libsaio/ati.c
Added from trunk, ErmaC and tonymacx86.com users:
{ 0x9440, 0x0851174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot },
{ 0x68BA, 0x31501682, CHIP_FAMILY_JUNIPER, "AMD Radeon HD 6770", kVervet },
{ 0x68BF, 0x31401682, CHIP_FAMILY_JUNIPER, "AMD Radeon HD 6750", kVervet },
{ 0x68C0, 0x395217AA, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5730", kNull },
{ 0x68C1, 0x02051025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x02961025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x030A1025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x033D1025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x03471025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x03561025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x03581025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x035A1025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x035C1025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x03641025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x03791025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x037E1025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68C1, 0x03821025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5750", kNull },
{ 0x68E4, 0x1426103C, CHIP_FAMILY_CEDAR, "AMD Radeon HD 6370M ", kNull },
{ 0x68E4, 0x397917AA, CHIP_FAMILY_CEDAR, "AMD Radeon HD 6370M ", kNull },
{ 0x6719, 0x21FD1458, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950", kGibba },
{ 0x6719, 0x186B174B, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950", kNull },
{ 0x6720, 0x04901028, CHIP_FAMILY_BARTS, "AMD Radeon HD 6970M", kElodea },
{ 0x6739, 0x03B41043, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed },
{ 0x6740, 0x1631103C, CHIP_FAMILY_TURKS, "AMD FirePro M5950", kNull },
{ 0x6740, 0x3388103C, CHIP_FAMILY_TURKS, "AMD Radeon HD 6770M", kNull },
{ 0x6741, 0x1688103C, CHIP_FAMILY_TURKS, "AMD Radeon HD 7690M", kNull },
{ 0x6758, 0x00121028, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes },
{ 0x6759, 0x20121787, CHIP_FAMILY_TURKS, "AMD Radeon HD 6570", kPithecia },
{ 0x6760, 0x00031179, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450M", kNull },
{ 0x6779, 0xE180174B, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450", kPithecia },

• Added the following missing AMD/ATI default card definitions:

i386/libsaio/ati.c
{ 0x944A, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot },
{ 0x9480, 0x00000000, CHIP_FAMILY_RV730, "ATI Mobility Radeon HD 4650 Series", kGliff },
{ 0x9553, 0x00000000, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kShrike },
{ 0x9581, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull },
{ 0x9583, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull },
{ 0x9588, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 XT Series", kNull },
{ 0x9589, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 3610 Series", kNull },
{ 0x9591, 0x00000000, CHIP_FAMILY_RV635, "ATI Radeon HD 3600 Series", kNull },
{ 0x68A1, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Mobility Radeon HD 5800 Series", kNomascus },
{ 0x68A8, 0x00000000, CHIP_FAMILY_CYPRESS, "AMD Radeon HD 6800M Series", kUakari },
{ 0x68BF, 0x00000000, CHIP_FAMILY_JUNIPER, "AMD Radeon HD 6700 Series", kVervet },
{ 0x68C0, 0x00000000, CHIP_FAMILY_REDWOOD, "AMD Radeon HD 6570M/5700 Series", kNull },
{ 0x68C1, 0x00000000, CHIP_FAMILY_REDWOOD, "AMD Radeon HD 6500M/5600/5700 Series", kNull },
{ 0x68E0, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Mobility Radeon HD 5400 Series", kEulemur },
{ 0x68E1, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Mobility Radeon HD 5400 Series", kEulemur },
{ 0x68E4, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 6300M Series", kNull },
{ 0x6750, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6600A Series", kNull },

• Added the following missing AMD/ATI chip family:

i386/libsaio/ati.c
Added CHIP_FAMILY_RV790 to chip_family_t;
Added "RV790" to chip_family_name[]

• Made the following cosmetic changes for AMD/ATI cards:

i386/libsaio/ati.c

• Changed all vendor names in radeon_cards to ATI as that would be contrary to what Apple would report.
• For any specific card configuration that contained a generic name using something like "ATI Radeon HD 4800 Series" changed it to the specific card name and removed "Series".
• Added "Series" to any generic card configuration to signify it's a generic and not card specific.
• Corrected a bunch of card names.

There is a standalone installer, available at tonymacx86.com/downloads. For bug reporting, feature requests, and general feedback please use the Chimera forum.

-MacMan & tonymacx86  

For discussions on this and other topics, register today at tonymacx86.com!

Chimera 1.7.0 Change Log

Back ported the following Chameleon commits:

• r1671 Updated credits
• r1674 Improved Multi-drive boot support from dmazar.
• r1710 Fix for kernel flags not being passed to kernel on RAID volumes.

Added the following AMD GPUs:

• 0x9440, 0x114A174B, CHIP_FAMILY_RV770, "Sapphire Radeon HD4870 Vapor-X", kCardinal
• 0x954F, 0x20081787, CHIP_FAMILY_RV710, "ATI Radeon HD 4350", kNull
• 0x6899, 0xE174174B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari
• 0x68A0, 0x043A1028, CHIP_FAMILY_CYPRESS, "ATI Mobility Radeon HD 5870", kNomascus
• 0x68B8, 0x21F61458, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet
• 0x68B8, 0x200A1787, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet
• 0x68BE, 0x22881787, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5750", kVervet
• 0x68F9, 0x010E1002, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur
• 0x68F9, 0x03741043, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur
• 0x68F9, 0x23401462, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur
• 0x68F9, 0xE145174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur
• 0x68F9, 0xE153174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur
• 0x6719, 0x0B001002, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950", kGibba
• 0x6719, 0x20101787, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950", kGibba
• 0x6720, 0x04BA1028, CHIP_FAMILY_BARTS, "AMD Radeon HD 6970M", kElodea
• 0x6738, 0x31071682, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed
• 0x6738, 0x31081682, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed
• 0x6738, 0x174B174B, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kBulrushes
• 0x6739, 0xAA881002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed
• 0x6740, 0x1D121043, CHIP_FAMILY_TURKS, "AMD Radeon HD 6730M", kNull
• 0x6760, 0x165A103C, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6470M", kNull
• 0x6760, 0x167D103C, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6470M", kNull
• 0x68A0, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800M Series", kNomascus
• 0x68BA, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 6770 Series", kVervet
• 0x6719, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950 Series", kGibbas

Added a change that should hopefully allow the ability to override kNull frame buffer definitions.

Added the following NVIDIA GPUs:

• 0x10DE06DF, "Tesla M2070-Q" 
• 0x10DE0DCD, "GeForce GT 555M" 
• 0x10DE0DCE, "GeForce GT 555M" 
• 0x10DE0DD6, "GeForce GT 550M" 
• 0x10DE0DDA, "Quadro 2000M" 
• 0x10DE0DEC, "GeForce GT 525M" 
• 0x10DE0DED, "GeForce GT 520M" 
• 0x10DE0DF4, "GeForce GT 450M" 
• 0x10DE0DF5, "GeForce GT 525M" 
• 0x10DE0DF6, "GeForce GT 550M" 
• 0x10DE0DF7, "GeForce GT 520M" 
• 0x10DE0DFA, "Quadro 1000M" 
• 0x10DE0E31, "GeForce GTX 485M" 
• 0x10DE0E3A, "Quadro 3000M" 
• 0x10DE0E3B, "Quadro 4000M" 
• 0x10DE1054, "GeForce GT 410M" 
• 0x10DE1057, "Quadro NVS 4200M" 
• 0x10DE107F, "NVIDIA GF119-ES" 
• 0x10DE10C5, "GeForce 405" 
• 0x10DE1201, "GeForce GTX 560" 
• 0x10DE1251, "GeForce GTX 560M"

Added the following cards to the NVIDIA memory detection bug workaround:

• GT 440 Device ID 0x0DE0 
• GT 525M Device ID 0x0DEC

There is a standalone installer, available at tonymacx86.com/downloads. For bug reporting, feature requests, and general feedback please use the Chimera forum.

-MacMan & tonymacx86  

For discussions on this and other topics, register today at tonymacx86.com!

Chimera 1.5.4 Change Log

It's been a busy couple of weeks since I released Chimera 1.5.0. I delayed this blog post due to the updates I had to make to fix and support additional AMD cards and the Facetime issue. This revision is based on  Chameleon 2.0 Revision 1394 which is the code base for the official release of Chameleon 2.0. Since Chimera 1.4 was released the Chameleon team has included some of what I did in Chimera 1.4 to the trunk. I have also have been supplying some fixes and enhancements to the Chameleon trunk to make future updates of Chimera easier.

The main features in this release are:

• Support for additional NVIDA and AMD video controllers
• Inclusion or correction fo some AMD frame buffer names 
• Facetime fix from olegpronin at insanelymac (of which I have added a new Boot key to bypass this fix if needed (thanks to Lnx2Mac for the idea.))
• Sandy Bridge HD Graphics support based on the work valv started to support the Mobile HD 3000 controller. I've enhanced it to support mobile and desktop controllers.

Here are the specific edits for this version and as a reminder, all lines starting with a dash will be the name of the affected file starting at the branch root.

General fixes and enhancements:
 - i386/boot2/boot.h
   Added #define kSkipFTFix  "SkipFTFix" for disabling the Facetime fix code.
 - i386/libsaio/ati.c
   Enhanced some of the debug messages for ports and frame buffers.
   Added a debug message to display the number of ports the cards VBIOS is reporting.
   Changed default frame buffer for the HD 6670 and HD 6450 to Bulrushes
   Added the following additional AMD cards:
  { 0x68BF, 0x220E1458, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 6750", kVervet },
        { 0x6738, 0x00D01002, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6870", kDuckweed },
        { 0x6738, 0x21FA1002, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6870", kDuckweed },

{ 0x6738, 0x21FA1458, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6870", kDuckweed },

{ 0x6738, 0x31031682, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6870", kDuckweed },

{ 0x6738, 0x31041682, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6870", kDuckweed },

{ 0x6738, 0xE178174B, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6870", kDuckweed },

{ 0x6738, 0x20101787, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6870", kDuckweed },

{ 0x6738, 0x23051787, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6870", kDuckweed },

{ 0x6739, 0x24411462, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6850", kDuckweed },

{ 0x6739, 0xE177174B, CHIP_FAMILY_BARTS,    "AMD Radeon HD 6850", kDuckweed },

{ 0x6758, 0x67581002, CHIP_FAMILY_TURKS,    "AMD Radeon HD 6670", kBulrushes },

{ 0x6758, 0x22051458, CHIP_FAMILY_TURKS,   "AMD Radeon HD 6670", kBulrushes },

{ 0x6758, 0x31811682, CHIP_FAMILY_TURKS,     "AMD Radeon HD 6670", kBulrushes },

{ 0x6758, 0x31831682, CHIP_FAMILY_TURKS,     "AMD Radeon HD 6670", kBulrushes },

{ 0x6758, 0xE1941746, CHIP_FAMILY_TURKS,     "AMD Radeon HD 6670", kBulrushes },

{ 0x6779, 0x64501092, CHIP_FAMILY_CAICOS,   "AMD Radeon HD 6450", kBulrushes },

{ 0x6779, 0xE164174B, CHIP_FAMILY_CAICOS,   "AMD Radeon HD 6450", kBulrushes },

 - i386/libsaio/fake_efi.c

   Added olegpronin's Facetime fix
   Added the ability to bypass this fix at boot time using the boot key of SkipFTFix=Yes
 - i386/libsaio/gma.c
   Added valv's code for Mobile HD 3000 Graphics support
   Added support for Mobile HD 2000
   Added support for desktop HD 2000 and HD 3000
   Added specific code for HD 2000 and HD 3000
   Added a work around for desktop HD 3000's to work with unpatched kexts or DSDT edits.
 - i386/libsaio/nvidia.c
   Added the following new device ID:
  { 0x10DE1086, "GeForce GTX 570" },

Chimera Specific Changes:
 - i386/boot2/prompt.c
   Changed Chameleon to Chimera and hardcoded version information
 - i386/libsaio/fake_efi.c
   Changed FIRMWARE_VENDOR from Chameleon 2.0 to Chimera 1.5

For bug reporting, feature requests, and general feedback please use the Chimera forum. 

-MacMan & tonymacx86 

For discussions on this and other topics, register today at tonymacx86.com!

Minimal DSDT Edits for Gigabyte Socket 1155 Motherboards

I started researching and testing what edits from my New Minimal DSDT Edits for Gigabyte Socket 1156 Motherboards were or weren't needed on the Socket 1155 boards. The good news is that the majority of the edits carry over, but some are not needed. For example, we don't need to inject anything for the USB ports to be fully recognized. But there are a couple of required Socket 1155 specific edits.

The following is a guide for editing the extracted DSDT. The first thing you will need to do is the required edits so that the DSDT will compile. They are:

1) "Reserved method must return a value"

 Add to the end of _WAK

        Return (Package (0x02)
        {
            0x00,
            0x00
        })
     
2) "Method local variable is not initialized"

 In Scope (\_SI)

Change both:

  Store (Local0, Local0)
 
 To:

 Store (0x00, Local0)

3) "Use of compiler reserved name"

 Replace all _T_ with T_

4) "Effective AML package length is zero"

 Change:

  Name (RPMV, Package (0x00) {})

 To:

  Name (RPMV, Package (Zero) {})

5) "Result is not used, operator has no effect"

 Change:

  Or (0x03, PARM)

 To:

  Or (PARM, 0x03, PARM)

The first required edit is to include Method DTGP for passing configuration parameters to OS X. Next up is renaming device names to follow Apple's conventions. They are renaming all PX40 to LPCB, PX43 to SBUS, all AZAL to HDEF, Device (IDE1) to Device (SATA) and it's sub-device ports from Device (PRIM) to Device (PRT0) and Device (SECD) to Device (PRT1), deleting Device (IDE2) (unused) and finally renaming the USB device names, USBE to EHC1 and USE2 to EHC2

Now that we have all of the correct device names now we need to add some missing information. For the SMBus we need to add the following to Device (SBUS) as a nested sub-device:

                Device (BUS0)
                {
                    Name (_CID, "smbus")
                    Name (_ADR, 0x00)
                    Device (DVL0)
                    {
                        Name (_ADR, 0x57)
                        Name (_CID, "diagsvault")
                        Method (_DSM, 4, NotSerialized)
                        {
                            Store (Package (0x02)
                                {
                                   "address",
                                    0x57
                                }, Local0)
                            DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                            Return (Local0)
                        }
                    }
                }

For ALC8xxHDA to work correctly we need to inject into Device (HDEF) codec information. Here is an example of what needs to be added for a board using and an ALC889 codec:

                Method (_DSM, 4, NotSerialized)
                {
                    Store (Package (0x04)
                        {
                            "layout-id",
                            Buffer (0x04)
                            {
                                0x79, 0x03, 0x00, 0x00   // decimal 889
                            },
                            "PinConfigurations",
                            Buffer (Zero)
                            {
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }

For other codecs you will need to change the layout-id to match your codec.

There is a problem with Audio break ups that can be corrected in the DSDT. The first is in Device (PIC) remove these two lines:

  IRQNoFlags ()
                {2}

The other fix for audio break ups is in Device (TMR) where we need to change:

                    Method (_CRS, 0, NotSerialized)
                    {
                        If (LGreaterEqual (OSFX, 0x03))
                        {
                            If (HPTF)
                            {
                                Return (ATT6)
                            }
                            Else
                            {
                                Return (ATT5)
                            }
                        }
                        Else
                        {
                            Return (ATT5)
                        }
                    }

To:
                    Method (_CRS, 0, NotSerialized)
                    {
                        Return (ATT6)
                    }

The next fix is to prevent kernel panics in AppleIntelCPUPowerManagement at boot time. This fix is easy; just change Method (_STA, 0, NotSerialized) to Return (0x0F) and to change Method (_CRS, 0, NotSerialized) to Return (ATT3).

The final edit is to allow you to use the power button to put the computer to sleep.  In Device (PWRB) change Name (_HID, EisaId ("PNP0C0C")) to Name (_CID, EisaId ("PNP0C0C")).

If you don't want to bother with these edits, you can download pre-edited DSDTs from the tonymacx86.com DSDT Database.

For discussions on this and other topics, register today at http://www.tonymacx86.com/

Creating a Bootable “DOS” USB Stick on a Hackintosh Without Windows or MS-DOS

A lot of manufacturers provide DOS only firmware updaters. If you have a dual boot system with Windows it’s a piece of cake. But the issue is how do you do this on a Hackintosh without Windows installed?  Well I have found a solution, FreeDOS, a free DOS-compatible operating system for IBM-PC compatible systems. 

What you need:

• USB drive greater than 16 MB
• FreeDOS Base CD
• Blank CD or CD-RW

Installation procedure:

1. Format the USB drive as a MBR/FAT volume
2. Burn the FreeDOS Base CD
3. Shut down OS X and disconnect all disk drives
4. Boot computer while ensuring that Legacy USB support is enabled in the BIOS and USB drive is connected
5. Boot from FreeDOS Base CD and follow instructions to install. It will install by default to the 1st drive it finds. In this case it’s the USB drive as it’s the only one connected.
6. Shutdown and reconnect all disk drives.
7. You now have a bootable “DOS” drive.

This drive is bootable and can be read and written to in OS X. You can copy any DOS based programs on to it and boot from it to run them.

For discussions on this and other topics, register today at tonymacx86.com!

Chimera v1.4.0 Change Log

It's good to see that the Chameleon team has started porting some of the changes I made from Chimera to the Chameleon 2.0 RC5 trunk. They recently did a major update and added significant new features in trunk revision 833. Some of the changes were enhanced and fixed Sandy Bridge support amongst others. So I went back and integrated my changes into that trunk version and created Chimera v1.4.0.

Starting with this version I will list in detail all changes I've made. All lines starting with a dash will be the name of the affected file starting at the branch root.

General fixes and enhancements:

Chimera 1.4.0 Installer available
at tonymacx86.com/downloads

- CHANGES
        Fixed typos
- doc/BootHelp.txt
        Added UseKernelCache=Yes|No
        Reworded some options
- TODO
        Fixed typos
- i386/boot2/boot.c
        Fixed typos in comments
        Reordered keys according to source file name
- i386/doc/README
        Fixed typos
- i386/libsaio/acpi_patcher.c
        In switch (Platform.CPU.Model)
                Removed nonexistent CPU model case 0x0D: // ?
                Redid comments for all case CPU_MODEL_ to provide actual CPU model names
- i386/libsaio/ati.c
        In static radeon_card_info_t  radeon_cards[]
                Removed duplicate blank lines
                Removed duplicate "ATI Radeon HD 5400 Series"
                Added additional AMD cards:
                        { 0x6739, 0x21F81458, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850",
kDuckweed },
                        { 0x6719, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950
                           Series", kNull },
                        { 0x6738, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870 Series", 
kDuckweed },
                        { 0x6739, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850 Series", 
kDuckweed },
                        { 0x673E, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6790 Series",
  kNull },
                Changed { 0x6718, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6900
                          Series", kNull },
                 to { 0x6718, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970 Series",
kNull },
- i386/libsaio/cpu.c
        Updated /* Mobile CPU */ to use MSR_IA32_PLATFORM_ID instead of a hex value
        Rearranged DBG info at end and added additional info
- i386/libsaio/cpu.h
        Added #define MSR_IA32_PLATFORM_ID 0x17
- i386/libsaio/memvendors.h
        Removed extra spaces in fromt of { 0, 0x01, "AMD"},
- i386/libsaio/nvidia.c
        Added comments to add device id blocks like // 0040 - 004F, // 0050 - 005F, etc.

        Added workaround code for GT 430 & 9600M GT memory detection from valv

        Added GT 420 to GT 430 & 9600M GT memory detection work around
        Added the following new device IDs from valv and Linux driver (some are already in v1.3.0):
                { 0x10DE0410, "GeForce GT 330" },
                { 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
                { 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
                { 0x10DE053E, "GeForce 7025 / nForce 630a" },
                { 0x10DE05ED, "Quadroplex 2200 D2" },
                { 0x10DE05F8, "Quadroplex 2200 S4" },
                { 0x10DE05FF, "Quadro FX 3800" },
                { 0x10DE0601, "GeForce 9800 GT" },
                { 0x10DE0603, "GeForce GT 230" },
                { 0x10DE060F, "GeForce GTX 285M" },
                { 0x10DE0619, "Quadro FX 4700 X2" },
                { 0x10DE061B, "Quadro VX 200" },
                { 0x10DE062D, "GeForce 9600 GT" },
                { 0x10DE062E, "GeForce 9600 GT" },
                { 0x10DE0631, "GeForce GTS 160M" },
                { 0x10DE0632, "GeForce GTS 150M" },
                { 0x10DE0635, "GeForce 9600 GSO" },
                { 0x10DE0637, "GeForce 9600 GT" },
                { 0x10DE0638, "Quadro FX 1800" },
                { 0x10DE063A, "Quadro FX 2700M" },
                { 0x10DE0651, "GeForce G 110M" },
                { 0x10DE0653, "GeForce GT 120M" },
                { 0x10DE0654, "GeForce GT 220M" },
                { 0x10DE0656, "GeForce 9650 S" },
                { 0x10DE065F, "GeForce G210" },
                { 0x10DE06E2, "GeForce 8400" },
                { 0x10DE06E3, "GeForce 8400 SE" },
                { 0x10DE06E6, "GeForce G100" },
                { 0x10DE06E7, "GeForce 9300 SE" },
                { 0x10DE06FB, "Quadro FX 370M" },
                { 0x10DE07E0, "GeForce 7150 / nForce 630i" },
                { 0x10DE07E1, "GeForce 7100 / nForce 630i" },
                { 0x10DE07E2, "GeForce 7050 / nForce 630i" },
                { 0x10DE07E3, "GeForce 7050 / nForce 610i" },
                { 0x10DE07E5, "GeForce 7050 / nForce 620i" },
                { 0x10DE0844, "GeForce 9100M G" },
                { 0x10DE0845, "GeForce 8200M G" },
                { 0x10DE0846, "GeForce 9200" },
                { 0x10DE0847, "GeForce 9100" },
                { 0x10DE0848, "GeForce 8300" },
                { 0x10DE0849, "GeForce 8200" },
                { 0x10DE084A, "nForce 730a" },
                { 0x10DE084B, "GeForce 9200" },
                { 0x10DE084C, "nForce 980a/780a SLI" },
                { 0x10DE084D, "nForce 750a SLI" },
                { 0x10DE084F, "GeForce 8100 / nForce 720a" },
                { 0x10DE0860, "GeForce 9400" },
                { 0x10DE0861, "GeForce 9400" },
                { 0x10DE0862, "GeForce 9400M G" },
                { 0x10DE0863, "GeForce 9400M" },
                { 0x10DE0864, "GeForce 9300" },
                { 0x10DE0865, "ION" },
                { 0x10DE0866, "GeForce 9400M G" },
                { 0x10DE0867, "GeForce 9400" },
                { 0x10DE0868, "nForce 760i SLI" },
                { 0x10DE086D, "GeForce 9200" },
                { 0x10DE086E, "GeForce 9100M G" },
                { 0x10DE086F, "GeForce 8200M G" },
                { 0x10DE087A, "GeForce 9400" },
                { 0x10DE0A22, "GeForce 315" },
                { 0x10DE0A2B, "GeForce GT 330M" },
                { 0x10DE0A2C, "NVS 5100M" },
                { 0x10DE0A2D, "GeForce GT 320M" },
                { 0x10DE0A35, "GeForce GT 325M" },
                { 0x10DE0A3C, "Quadro FX 880M" },
                { 0x10DE0A64, "ION" },
                { 0x10DE0A67, "GeForce 315" },
                { 0x10DE0A68, "GeForce G105M" },
                { 0x10DE0A69, "GeForce G105M" },
                { 0x10DE0A6A, "NVS 2100M" },
                { 0x10DE0A6C, "NVS 3100M" },
                { 0x10DE0A6E, "GeForce 305M" },
                { 0x10DE0A6F, "ION" },
                { 0x10DE0A70, "GeForce 310M" },
                { 0x10DE0A71, "GeForce 305M" },
                { 0x10DE0A72, "GeForce 310M" },
                { 0x10DE0A73, "GeForce 305M" },
                { 0x10DE0CA0, "GeForce GT 330 " },
                { 0x10DE0CA2, "GeForce GT 320" },
                { 0x10DE0CA4, "GeForce GT 340" },
                { 0x10DE0CA7, "GeForce GT 330" },
                { 0x10DE0CAC, "GeForce 315" },
                { 0x10DE0CAF, "GeForce GT 335M" },
                { 0x10DE0CB0, "GeForce GTS 350M" },
                { 0x10DE0CBC, "Quadro FX 1800M" },
                { 0x10DE0DE0, "GeForce GT 440" },
                { 0x10DE0DE5, "GeForce GT 530" },
                { 0x10DE1040, "GeForce GT 520" },
                { 0x10DE1050, "GeForce GT 520M" },
                { 0x10DE1081, "GeForce GTX 570" },        Updated with model name
                { 0x10DE1082, "GeForce GTX 560 Ti" },   Updated with model name
                { 0x10DE1088, "GeForce GTX 590" },
                { 0x10DE10C3, "GeForce 8400 GS" },
                { 0x10DE1200, "GeForce GTX 560 Ti" },
                { 0x10DE1244, "GeForce GTX 550 Ti" },
                { 0x10DE1245, "GeForce GTS 450" },
- i386/libsaio/platform.h
        Added additional info to comments for #define CPU_MODEL_
- i386/libsaio/smbios.c
        Updated comments on all case CPU_MODEL_ to provide actual CPU model names
- i386/libsaio/smbios_getters.c
        Updated comments on all case CPU_MODEL_ to provide actual CPU model names
        Removed all references to nonexistent CPU models:
                case 0x0D: // ?
                case 0x19: // Intel Core i5 650 @3.20 Ghz
        Added workaround to not calculate qpibusspeed for LGA 1155 and LGA 1156 CPUs
           and report a sane value
        Added Xeon model detection and reporting to CPU_MODEL_FIELDS:
        Broke out case CPU_MODEL_SANDY_XEON: to report Xeon CPU

Chimera Specific Changes:

- i386/boot2/Makefile
        git revision workaround
- i386/boot2/prompt.c
        Changed Chameleon to Chimera
- i386/libsaio/fake_efi.c
        Changed FIRMWARE_VENDOR from Chameleon 2.0.0 to Chimera 1.4.0

For bug reporting, feature requests, and general feedback please use the Chimera forum. 

-MacMan & tonymacx86 

For discussions on this and other topics, register today at tonymacx86.com!

Chimera v1.1.0 Source Pedigree and Enhancements

Most of you know about Chimera based on the announcement we made on the tonymacx86 Blog. A few of you are interested in what I did and what is different in Chimera compared to the Chameleon trunk. Without getting too deep into the code, I will attempt to explain in general terms these differences. I will be explaining the changes based on v1.1.0 r753 as this was the first source version released.

I wanted to start with the trunk version as I know that code is clean and stable. The first few things I did was fix a few spelling errors in TODO and i386/doc/README. No big deal, but I think something that was overdue. Next, I went through all of the source files. I cleaned up the comments for readability to make sure they all lined up properly. Here are the list of files that I did this to:

i386/boot2/boot.h
i386/libsa/memory.h
i386/libsaio/bootstruct.h
i386/libsaio/cpu.h
i386/libsaio/fdisk.h
i386/libsaio/memvendors.h
i386/libsaio/nvidia.c
i386/libsaio/smbio_patcher.c
i386/libsaio/smbio_patcher.h
i386/libsaio/spd.c

Again, not a big deal, but to make it easier for me to read the code.

So now it was time to start merging features. I decided to start with Kabyl's ATI support. For this I had to update doc/BootHelp.txt to include his 2 new boot keys. I also added the two actual boot keys to i386/boot2/boot.h. Then in i386/libsaio/, I replaced the trunk ati.c with Kabyl's. Added his ati_reg.h and removed ati.h. Then I added Kabyl's changes to pci.c, pci.h and pci_setup.c.

Next was merging valv's NVIDIA changes. For that I added 2 new NVIDIA keys to i386/boot2/boot.h. Then in i386/libsaio/nvidia.c I used a combination of trunk, valv and new device ID's I could find to support as many cards as possible in NVKnownChipsets. I then used valv's #define NVIDIA_ROM_SIZE 0x20000 and  static uint8_t default_dcfg_0[], static uint8_t default_dcfg_1[], and static uint8_t default_NVPM[]. I also used his improved video RAM detect code, workaround code for gt 430 & 9600M GT and support for user supplied @0,display-cfg and @1,display-cfg keys.

The final changes were in adding Sandy Bridge support. For this I used some of valv's code but added a bunch of my own. From valv I used his setup features which required using his CPU Features in platform.h. Where I also took his #define bit definitions. Then in cpu.h I used his additional MSR defines and static inline __attribute__((always_inline)) void wrmsr(unsigned val, msr_t msr), typedef struct msr_struct and static inline __attribute__((always_inline)) msr_t rdmsr(unsigned val). And finally some of his CPU debug messages and formatting at the end of cpu.c.

So as documented above, I've reused a bunch of code from Kabyl and valv. Now let's discuss the changes I did. The first thing is in platform.h where I added #define CPU_MODEL_DUNNINGTON 0x1D and #define CPU_MODEL_SANDY_BRIDGE 0x2A. Then in cpu.c I changed all p->CPU.Model from using hex values to defined values from platform.h. I did this to make troubleshooting easier- as I don't know all of the CPUs model codes by heart. I then removed p->CPU.Model == 0x1f as I can find no reference anywhere of this CPU model. I then went and redid  if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) to add Sandy Bridge support.

When testing the code I found that cpu.c was reporting 8 cores and 16 threads for Core i and Sandy Bridge CPUs. It took a bit of digging but I found that in the original code the value for them was being extracted from a Machine Specific Register (MSR) that was returning the Maximum # of addressable IDs for logical processors in this physical package and Maximum # of addressable IDs for processors cores in this physical package. So I did a bunch of testing and research and found that there is an undocumented MSR, MSR_CORE_THREAD_COUNT that will return the correct values. I used that in Chimera v1.0.0 r750 but we soon learned that that isn't a valid MSR on Penryn or earlier CPU models.  So in v1.1.0 I added the following code to set the number of cores and threads correctly:

if ((p->CPU.Vendor == 0x756E6547 /* Intel */) &&
    (p->CPU.Family == 0x06) && (p->CPU.Model >= 0x1a)){

msr = rdmsr64(MSR_CORE_THREAD_COUNT);            // Undocumented MSR

p->CPU.NoCores = bitfield((uint32_t)msr, 31, 16);     // Get actual values

p->CPU.NoThreads = bitfield((uint32_t)msr, 15,  0);   // Get actual values

} else {  // Use previous method for Cores and Threads

p->CPU.NoThreads = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);

p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;

}

I also changed the Mobile CPU test from using a hex value to the MSR name MSR_IA32_Platform_ID.

Next up was  i386/libsaio/acpi_patcher.c. Here I removed the case 0x0D: statement as this CPU model family Dothan, pre-dates the Core family. I also added a case CPU_MODEL_SANDY_BRIDGE: and added comments for what each CPU model covers. So for example:

 case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm).

In  i386/libsaio/spd.c I changed smbus_controllers[] to report "5 Series" instead of "P55" and added {0x8086, 0x1C22, "6 Series",read_smb_intel }.

The final source file to modify was i386/libsaio/smbios_patcher.c. Here I also added better CPU comments like in acpi_patcher.c. I also changed all reference of "Apple Computer, Inc." to "Apple Inc.",  fixed MacPro3,1 "SMboardproduct" and MacPro4,1 "SMboardproduct" to use the correct board numbers and finally reorganized the system order to MacBook, MacBook Pro, mini, iMac8,1, iMac11,1 MacPro3,1 and MacPro4,1. The I removed all instances of case 0x19: // Intel Core i5 650 @3.20 Ghz as I couldn't find any references to this CPU model and the description didn't match the model value. I also removed  case 0x0D:  and added case CPU_MODEL_SANDY_BRIDGE:. Other changes were adding DBG("FSBFrequency %d\n", Platform.CPU.FSBFrequency); and changing DBG("qpimult %x\n", qpimult); to display in hex instead of decimal. The final changes were hard coding the Processor Interconnect speed for Sandy Bridge CPUs to 4.8 GT/s instead of the incorrect calculated value. Finally I redid sm_get_cputype to correctly handle all possible CPU types, including Xeons.

In addition, I took from tonymacx86.com forum user AndyStubbs his code additions to support the AMD Radeon HD 6000 cards and his fix to i386/libsaio/smbios_patcher.c for DMI table overflow on Sandy Bridge systems. Thanks Andy.

Going forward the plan is to keep Chimera updated with trunk revisions in addition to adding new features and bug fixes.

I will post further code changes when I release new versions. So stay tuned for updates.

Further Reading:
Chimera Source
Chimera: Unified Chameleon Bootloader
Chimera Now An Official Chameleon Branch
Chimera 1.1 Update
Chimera 1.3 Update
Chimera at tonymacx86 Wiki